SiFive has introduced the P550, a new processor microarchitecture that represents progress in bringing RISC-V into higher performance computing applications. The P550 aims to deliver 30% better performance while using less than half the silicon area compared to Arm's Cortex-A75 processor.
The P550 features a 13-stage pipeline with 3-wide out-of-order execution capabilities, allowing it to process instructions in parallel and work around stalled operations. This marks an evolution from SiFive's earlier U87 design, bringing improved maturity to their out-of-order architecture.
Key features of the P550 include:
- 32KB instruction cache and 32KB data cache
- 256KB L2 cache per core
- Up to 8MB shared L3 cache
- Support for up to 4 cores per cluster
- Branch prediction with 9.1KB branch history table
- Two address generation units (one for loads, one for stores)
The processor shows competitive branch prediction capabilities compared to the Arm Cortex-A75, particularly when handling longer branch patterns with fewer branches. However, its 32-entry branch target buffer is relatively modest compared to high-performance designs.
In terms of execution resources, the P550 provides flexible integer processing with multiple ports and adequate scheduling capacity. The floating point unit handles common operations like adds, multiplies and fused multiply-adds with 4-cycle latency.
The memory subsystem employs a two-level translation lookaside buffer (TLB) for address translation, though with relatively small 32-entry L1 TLBs. One notable weakness is poor handling of unaligned memory accesses, which can take hundreds of cycles to process.
While not matching the absolute performance of high-end processors from Intel and AMD, the P550 represents meaningful progress for the RISC-V ecosystem. It demonstrates SiFive's growing capability in designing out-of-order processors while maintaining power and area efficiency targets suitable for embedded applications.
The P550 provides a foundation for SiFive to build upon as they work toward more sophisticated designs like the recently announced P870. For the RISC-V instruction set architecture to gain broader adoption, continued evolution of processor implementations like the P550 will be key.